Commonly assigned U.S. Pat. No. 4,945,538 discloses an analog-to-digital converter (ADC) that receives a clock signal from a phase-locked loop oscillator and converts the analog signal to digitized sample values at successive sample times. To eliminate phase error, differential delay between the clock signal and analog signal is removed by use of a discrete delay element, such as a digital chip of the type that permits manual setting of delays in increments as low as one tenth of nanosecond.
There is need for a method and apparatus that reliably eliminates delay due to phase error between the clock signal and analog input signal in a signal processing channel irrespective of the degree the signals are initially out of phase and despite the presence of noisy digitized sample values of the analog signal.